Crystalline silicon photovoltaic (PV) modules, as of 2012, account for approximately at least 85% of the overall global PV annual demand market and cumulative globally installed PV capacity. The manufacturing process for crystalline silicon PV is based on the use of crystalline silicon solar cells, starting with mono-crystalline or multi-crystalline silicon wafers made of czochralski (CZ) silicon ingots or cast silicon bricks. Non-crystalline-silicon-based thin film PV modules (for example CdTe, CIGS, organic, and amorphous silicon PV modules) may offer the potential for low cost manufacturing process but typically provide much lower conversion efficiencies (in the range of up to about 14% in STC module efficiency) for commercial thin-film PV modules as compared to the mainstream crystalline silicon PV modules (which may provide module efficiencies in the range of approximately 14% up to about 20%, and mostly in the range of about 14% to 17%), and an unproven long-term track record of field reliability as compared to well-established crystalline silicon solar PV modules. The leading-edge crystalline silicon PV modules offer superior overall energy conversion performance, long-term field reliability, non-toxicity, and life cycle sustainability compared to various other PV technologies. Moreover, recent progress and advancements have driven the overall manufacturing cost of crystalline silicon PV modules to below $0.80/Wp. Disruptive monocrystalline silicon technologies—such as high-efficiency thin monocrystalline silicon solar cells fabricated using reusable crystalline silicon templates, thin (e.g., crystalline silicon absorber thickness from approximately 10 μm up to about 100 μm, and typically ≦70 μm) epitaxial silicon, thin silicon support using backplane attachment/lamination, and porous silicon lift-off technology—offer the promise of high-efficiency (solar cell and/or module efficiencies of at least 20% under Standard Test Conditions or STC) and PV module manufacturing cost at well below $0.50/Wp at mass manufacturing scale.
Current crystalline silicon (or other semiconductor absorber material) solar cell structures and processing methods often suffer from several disadvantages relating to cell bow and cell cracking/breakage during and/or after cell processing as well as during the operation of crystalline silicon PV modules installed in the field. Solar cell processing often induces significant stresses (e.g., thermal and/or mechanical stresses) on a semiconductor substrate which may lead to thermally-induced warpage and crack generation and propagation (by thermal cycling or mechanical stresses). Bowed or non-planar solar cell substrates pose significant challenges and possible manufacturing yield degradation during solar cell processing (such as during processing of crystalline silicon solar cells), and may present requirements for clamping down the solar cell substrate and/or the substrate edges onto a supporting substrate carrier to flatten the cell substrate during manufacturing process. Flattening solutions may complicate the solar cell manufacturing process, resulting in increased manufacturing cost and/or some manufacturing throughput and yield compromises. Bowed or non-planar solar cell substrates may further result in cell microcracks and/or breakage problems during module lamination and also subsequently during the PV module operation in the field (resulting in PV module power degradation or loss). These problems may be further aggravated in larger area solar cells, such as the commonly used 156 mm×156 mm format (square or pseudo square) solar cells.
Further, conventional solar cells, particularly those based on an interdigitated back-contact or IBC design, often require relatively thick metallization patterns—due to the relatively high cell electrical current—which may add complexity to cell processing, increase material costs, and add significant physical stresses to the cell semiconductor material. Thermal and mechanical stresses induced by relatively thick (e.g., in the thickness range of 10's of microns for IBC cell metallization) metallization patterns on the solar cell frontside and/or backside, coupled with the coefficient of thermal expansion or CTE mismatch between conductive metals (e.g., plated copper used for IBC solar cells or screen-printed aluminum-containing and/or silver-containing metallization pastes used for conventional front-contact solar cells) and semiconductor materials (e.g., thin crystalline silicon absorber layer) may substantially increase the risk of producing microcracks, cell breakage, and cell bowing during cell processing (i.e., during and after cell metallization) and module processing (during and after cell-to-cell interconnections and module lamination assembly) as well as during field operation of the installed PV modules (i.e., due to weather conditions, temperature changes, wind-induced and/or snow-load-induced and/or installation-related module bending stresses).
Additionally, crystalline silicon modules often utilize relatively expensive external bypass diodes, which must be capable of handling relatively high forward-biased electrical currents in the range of approximately several amperes up to about 10 amperes and relatively high reverse bias voltages in the range of approximately 10 volts to 20 volts, in order to eliminate hot-spot effects caused by the partial or full shading of solar cells and to prevent the resulting potential solar cell and module reliability failures. Such shade-induced hot-spot phenomena, which are caused by reverse biasing of the shaded cell or cells in a PV module, may permanently damage the affected PV cells as well as the PV module encapsulation material and cell-to-cell interconnections, and even cause fire hazards, if the sunlight arriving at the surface of the PV cells in a PV module is partially blocked or not sufficiently uniform within the PV module—for instance, due to full or even partial shading of one or a plurality of solar cells. Bypass diodes are often placed on sub-strings of the PV module—typically one external bypass diode per sub-string of 20 solar cells in a standard 60-cell crystalline silicon solar module with three 20-cell sub-strings or one external bypass diode per sub-string of 24 solar cells in a 72-cell crystalline silicon solar module with three 24-cell sub-strings, while many other module formats and configurations with different numbers of embedded solar cells are possible for modules with any number of cells. This connection configuration with external bypass diodes across the series-connected cell strings prevents the reverse bias hot spots due to any shaded cells and enables the PV modules to operate with a relatively high degree of reliability throughout their lifetime under various real life shading or partial shading and soiling conditions. In the absence of solar cell shading or soiling, each cell in the string essentially acts as an electrical current source with relatively matched electrical current values with the other cells in the series-connected string of cells, with the external bypass diode in the sub-string being reversed biased with the total voltage of the sub-string in the module (for example, 20 cells in a series-connected string create approximately about 10V to 12V reverse bias across the bypass diode in a crystalline silicon PV system). With shading of a cell in a string, the shaded cell is reverse biased, turning on the bypass diode for the sub-string containing the shaded cell, thereby allowing the current from the good/non-shaded solar cells in the non-shaded sub-strings to flow in the external bypass circuit. While the external bypass diodes (typically three external bypass diodes included in the standard mainstream 60-cell crystalline silicon PV module junction box) protect the PV module and cells in case of shading of the cells, they can also actually result in significant loss of power harvesting and energy yield for the installed PV systems.
Currently, a majority of silicon solar cells are made using p-type (e.g., boron doped) crystalline silicon wafers (both multi-crystalline and mono-crystalline). Such cells are fragile and may break easily (and thus often must be packaged in rigid, framed, glass-covered modules), suffer from efficiency limits (typical p-type cell efficiency is limited to about 20%), efficiency degradations (such as Light-Induced Degradation or LID) due to iron boron (Fe—B) and boron-oxygen (B—O) pairings. Much work is being invested into developing foundation technology and transitioning to n-type (e.g., phosphorus doped) starting wafers which do not suffer from the same degradations and enable higher efficiency cells as compared to p-type starting wafers.
Further, the majority of solar modules installed or being produced utilize multi-crystalline or mono-crystalline silicon solar cells which are front contact cells (with frontside or sunnyside fingers and busbars). Such front contact cells may suffer from optical shading losses cause by front side metallization, including metallization fingers and busbars. Back contact architectures circumvent this problem.
The highest efficiency back contact cells employ interdigitated back-contact (IBC), back junction architectures which enable close proximity between the harvested carriers in the emitter and the terminals and also allow for lightly doped front surfaces which provide good blue response of the cells. Moreover, n-type wafers used for back-contact/back-junction (IBC) solar cells typically provide much higher minority carrier lifetimes compared to p-type wafers, resulting in additional higher cell efficiency upsides.
For best efficiency performance, back contact back junction IBC solar cells typically require very high minority carrier lifetime wafers—thus higher-lifetime n-type wafers are more suitable than p-type wafers for IBC cells. This may be to a large extent owed to the fact that the mean path that the generated minority carriers (for instance, holes in the case of n-type wafers and n-type IBC cell base) travel to be collected at the emitter junction located at the rear side of the cell is relatively large due to the distance to the rear collecting junction terminal from the cell frontside which is governed by the thickness of the wafer or semiconductor absorber layer.
While a certain thickness of the wafer (or semiconductor absorber) is beneficial for effectively harvesting a large fraction of infrared photons (such as those with energies closer to the bandgap energy of crystalline silicon), there is a diminishing return for value-add light absorption with larger absorber thickness, and both bulk recombination losses and the increased travel distance for the generated minority carriers (which are prone to recombination losses) lead to a deterioration of the overall cell efficiency performance as cell absorber thicknesses increase more than a certain optimum range, for example in the range of approximately 20 and 90 μm for mono-crystalline silicon, depending on the starting wafer quality (minority carrier lifetime or diffusion length). Correspondingly, from a cell efficiency performance point of view, crystalline silicon absorber thicknesses between approximately 20 and 90 μm may be optimal—the actual optimal thickness value depending on the absorber material quality as measured by minority carrier lifetime or diffusion length, and may be somewhat smaller than 20 μm or larger than 90 μm. The practical limitation to producing high-efficiency crystalline silicon cells using very thin wafers (e.g., ≦120 μm thickness for 156 mm×156 mm wafers) is the mechanical yield of such wafers throughout the cell manufacturing process (as well as subsequent module lamination process). The mechanical yield may be decreased due to breakage of such thin wafers during cell fabrication processes and handling, such as screen printing and wet processes, as well as due to breakage from excessive film stress or excessive bow, especially as back contact cells typically require very thick high-conductivity (e.g., plated copper) backside metallization (often many tens of microns thick plated copper to carry the relatively large cell currents, at low voltage, across inter-digitated back-contact, IBC, fingers).
The need for such thick metallization often requires the use of plating, such as electroplating, of Cu or stacks of Ni, Cu and Sn of the metal structures. Introducing electroplating, including copper electroplating, into production has been a substantial technological challenge for solar companies, none the least because of the inherent risk of intrinsic metal contamination of the silicon absorber layer with the metal from the plating solution or during further processing or aging. Moreover, copper plating for IBC cells may require multiple process steps (for example: formation of PVD seed layer, screen printed resist pattern, copper-nickel-tin electroplating, strip resist pattern, wet etch exposed seed) and has significant consumable costs as well as additional fab facilities CAPEX/OPEX costs to support the back-end plating line. The IBC cell requirement for relatively thick plated copper metallization also presents significant risks in terms of stresses introduced by the thick copper due to the thermal (CTE) mismatch between the relatively thick (e.g., 30 to 80 μm thick) plated copper layer and silicon.
These constraints as well as others have kept manufacturing costs for desirable back contact IBC cell architectures relatively high and limited mass adoption.